REF DES · U1 — gbra.dev

GERMÁN BRAVO LÓPEZ

FPGA Verification Engineer @ ASML · Eindhoven, NL

I design and verify digital hardware — RTL, UVM and the systems around it. Working on hdlpkg, a package manager that brings software-grade dependency management to HDL IP.

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01 — General Description

Digital hardware, end to end.

I'm a digital design and verification engineer working on FPGA and ASIC-class systems. My day-to-day is RTL in SystemVerilog and VHDL, UVM testbenches, and the tooling that keeps large hardware projects sane.

That last part turned into hdlpkg — an open-source package manager and dependency resolver for HDL IP, bringing the ergonomics of cargo, pip and npm to hardware design reuse.

I hold a Master's degree in Digital Architectures and Embedded Systems from the Universidad Politécnica de Madrid and a Bachelor's degree in Industrial Electronic Engineering from the Universidad de Granada. I'm also certified in UVM (Doulos) and SystemVerilog (Siemens EDA).

02 — Bill of Materials

Selected projects

PKG-MGR Python

hdlpkg

A package manager and dependency resolver for HDL IP cores — the ergonomics of cargo/pip/npm, for hardware design reuse.

FEATURED
APP-DESK C++ · Qt

laideal

Management software for a dry-cleaning business — a full desktop application in C++.

SOFT-CORE VHDL

custom_microcontroller

A microcontroller designed from scratch in VHDL — datapath, control unit and instruction set.

DSP-FPGA VHDL

image_filtering

Master's thesis: real-time image filtering accelerated on FPGA fabric.

SIM-MODEL MATLAB

battery_model

Bachelor's thesis: electrochemical modeling of Li-ion cells in MATLAB.

view all repositories on github →

03 — Pin Map

Capabilities

BANK 0 — RTL
  • 00 SystemVerilog
  • 01 VHDL
  • 02 RTL design
  • 03 Digital architecture
  • 04 FSM / datapath
BANK 1 — VERIF
  • 00 UVM
  • 01 Testbench design
  • 02 Functional coverage
  • 03 Assertions (SVA)
  • 04 Simulation
BANK 2 — TOOLS / SW
  • 00 Python
  • 01 C / C++
  • 02 MATLAB
  • 03 Git
  • 04 Linux
  • 05 CI / packaging
BANK 3 — DOMAIN
  • 00 FPGA acceleration
  • 01 Embedded systems
  • 02 DSP
  • 03 Communication protocols
  • 04 IP / design reuse

04 — Timing Diagram

Experience & education

  1. FPGA Verification Engineer

    ASML · Eindhoven, NL

    Digital design and UVM verification for high-tech lithography systems.

  2. Creator — hdlpkg

    Open source

    A package manager and dependency resolver for HDL IP cores. → hdlpkg.io

  3. UVM Adopter · SystemVerilog Fundamentals

    Doulos · Siemens EDA

    Professional certifications in constrained-random, coverage-driven verification.

  4. M.Sc. — Digital Architectures & Embedded Systems

    Universidad Politécnica de Madrid

    Master's thesis: real-time image filtering on FPGA.

  5. B.Sc. — Industrial Electronic Engineering

    Universidad de Granada

    Bachelor's thesis: electrochemical modeling of Li-ion batteries.

05 — I/O Ports

Get in touch

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